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MB86R02 'Jade-D' Hardware Manual V1.64
Pin multiplex mode #5
CMPX_MODE_3[1:0],
CMPX_MODE_2[1:0]
Functional Group ->
Pin Name:
TSG_4
TSG_5
TSG_6
TSG_7
TSG_8
TSG_9
TSG_10
TSG_11
TSG_12
*
Initial state for ES1
** Initial state for ES2
35.3 PU/PD added
Please note that the pins described in the following table have been modified in version ES2 of the
MBR02 'Jade-D' device (a pull-up or pull-down has been added).
DISP1
DCLKIN1
SYSTEM
PLLTDTRST
DISP0
TSG_4
CAP0
VIN0_4
CAP0
VIN0_5
CAP0
VIN0_0
CAP0
VIN0_6
CAP0
VIN0_1
CAP0
CCLK0
CAP0
VIN0_2
CAP0
VIN0_7
CAP0
VIN0_3
CAP1
CCLK1
CAP1
VINHSYNC1
MLB
MLB_CLK
CAN
CAN_RX1
CAN
CAN_RX0
SPI(s)Host
HOST_SPI_SCK
SPI(s)Host
HOST_SPI_DI
SPI(s)Host
HOST_SPI_SS
35-2
First MUX Function
{"00",
"XX"} */**
TCON[12:5]
st
1
Function:
TSG_4
TSG_5
TSG_6
TSG_7
TSG_8
TSG_9
TSG_10
TSG_11
TSG_12
D
B2
I
Video output interface 1 dot clock input
D
Test pin
E4
I
Pull up the pin to VDDE, via high resistance
D
W1
O
TCON Timing Signal 4
D
AB1
I
Video Capture Data Input 0 bit 4
D
AB2
I
Video Capture Data Input 0 bit 5
D
AC1
I
Video Capture Data Input 0 bit 0
AB3
D
I
Video Capture Data Input 0 bit 6
D
AC2
I
Video Capture Data Input 0 bit 1
AD1
D
I
Video Capture 0 Clock
D
AC3
I
Video Capture Data Input 0 bit 2
D
AB4
I
Video Capture Data Input 0 bit 7
AC4
D
I
Video Capture Data Input 0 bit 3
D
AF2
I
Video Capture 1 Clock
AC6
D
I
Video Capture 1 Horizontal Synchronisation
D
AE7
I
Media LB Clock Pin
D
AF9
I
CAN Reception 1
D
AD9
I
CAN Reception 0
D
AF11
I
HOST SPI Clock
AE11
D
I
HOST SPI Data Input (MOSI)
D
AC11
I
HOST SPI Slave Select
FUJITSU PROPRIETARY AND CONFIDENTIAL
Second MUX Function
{"01",
"0X"}
GPIO[7:0]
nd
2
Function:
DCLKIN0
GPIO_PD_0
GPIO_PD_1
GPIO_PD_2
GPIO_PD_3
GPIO_PD_4
GPIO_PD_5
GPIO_PD_6
GPIO_PD_7
Third MUX Function
ES1: {"10","0X"}
ES2: {"10","XX"}
APIX1_SB[5:0]
rd
3
Function:
DCLKIN0
ES1: GPIO_PD_0
ES2: CONST0
ES1: GPIO_PD_1
ES2: CONST0
APIX1_SB_0
APIX1_SB_1
APIX1_SB_2
APIX1_SB_3
APIX1_SB_4
APIX1_SB_5
-
PD
-
PU
L
PD
HiZ
PD
HiZ
PD
HiZ
PD
HiZ
PD
HiZ
PD
-
PD
HiZ
PD
HiZ
PD
HiZ
PD
HiZ
PD
-
PD
-
PD
HiZ
PD
HiZ
PD
HiZ
PU
HiZ
PU
HiZ
PU
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