Display Controller; Overview - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

18.6 Display Controller

18.6.1 Overview

The display and capture controllers in MB86R02 'Jade-D' have the structure shown below.
VIN0[7:0]
CCLK0
VINHSYNC0
VINVSYNC0
VINFID0
RI1[7:2]
GI1[7:2]
BI1[7:2]
CCLK1
VINHSYNC1
VINVSYNC1
VINFID1
1) Two independent sets of display controller and capture controller
This parallel structure is the same as in the Carmine GDC.
Each controller is the same as CORAL PA and can display up to six layers.
2) Two video outputs are used as two independent displays or two synchronous displays
Color component precision is 6bit
3) Video synchronous PWM shares GVi output
This PWM is based on a 12 bit counter and is synchnonous with the video clock.
The Hsync and Vsync signala can be used to reset the count.
4) Two independent capture inputs
Both ports accept ITU-656 and ITU-601 format, in parallel.
Only one port accepts the RGB666 format.
18-16
Disp Controller 0
video timing
controller
capture video data
controller 0 processor
capture video data
controller 1 processor
video timing
controller
AXI bus Disp Controller 1
SDRAM-IF
SDRAM
DCLKO0
VSYNC0
HSYNC0
DE0 / CSYNC
GV0 / VPWM0
DOUTR(G)(B)0_x
x
D1OUTR(G)(B)0_
HSYNC1
VSYNC1
DCLKO1
DE1 / CSYNC
GV1 / VPWM1