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MB86R02 'Jade-D' Hardware Manual V1.64
9 Interrupt Request Controller (IRC)
This chapter explains the interrupt controller's function and operation.
9.1 Overview
IRC is composed of three channels (IRC0, IRC1 and IRC2). IRC0/1/2 decides the priority of the IRQ
source up to 32 factors respectively, and notifies the ARM core the IRQ source with the highest
priority as IRQ interrupt. Therefore, IRC0/1/2 has a set register of the interrupt level permitted from a
set register and the ARM core of the priority of the IRQ factor.
Note:
The IRQ interrupt decided by IRC1 is accepted as an interrupt factor of IRQ6 of IRC0. Therefore, the
priority is decided by setting of IRC1 and setting IRQ6 of IRC0 as for all IRQ sources allocated in
IRC1.
Note:
The IRQ interrupt decided by IRC2 is accepted as an interrupt factor of IRQ5 of IRC0. Therefore, the
priority is decided by setting of IRC2 and setting IRQ5 of IRC0 as for all IRQ sources allocated in
IRC2.
As for the IRQ vector defined in ARM926EJ-S, the factor of the vector table can certain the expansion
to 32 by IRC though only "0×18". When the IRQ interrupt is asserted to the ARM core, the address of
the interrupt vector table corresponding to the IRQ interrupt factor is generated during the register,
and displayed. The IRQ interrupt handler should refer from "0×18" to the vector table of the expansion
that was able to be certained further.
There is FIQ by the source and is no preference circuit for one. For the interrupt controller, the timing
of the FIQ factor is controlled, and the attribute is transmitted to the ARM core as nFIQ assert.
In addition, the interrupt controller provides with the delay interruption controller and the HOLD
request cancellation demand circuit, and provides with the interrupt wake up circuit from stop/sleep
mode composed of the clock control circuit.
The interrupt controller is connected with the APB bus.
9.2 Features
The interrupt controller has the following features.
•
It is 3 channels built-in as for IRC that can correspond to the interrupt request up to 32 factors.
•
IRQ interrupt priority is decided, and it transmits to ARM926EJ-S.
•
Enable/mask of expansion IRQ interrupt
•
Expansion IRQ vector address is displayed.
•
The signal for the return from the stop mode is supplied to CRG (clock/reset generator).
•
The software interrupt can be issued by the register access.
9-1
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