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MB86R02 'Jade-D' Hardware Manual V1.64
Reset value
Bit 30 - 0
SPGMKOFF10
Mask bits: 0b=include bit in position matching, 1b= do not include this bit in position matching
DIR_SPG11PosOn
Register address
BaseAddress + 4B4
Bit number
31
Field name
SPGPSON_TOGGLE11
R/W
RW
Reset value
0
Sync pulse generator 11, 'Switch on' position
Bit 31
SPGPSON_TOGGLE11
toggle enable: 0b=disable, 1b=enable
Bit 30 - 16
SPGPSON_X11
X scan position
Bit 15
Reserved
Do not modify
Bit 14 - 0
SPGPSON_Y11
Y scan position
DIR_SPG11MaskOn
Register address
BaseAddress + 4B8
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Bit 30 - 0
SPGMKON11
Mask bits: 0b=include bit in position matching, 1b= do not include this bit in position matching
DIR_SPG11PosOff
Register address
BaseAddress + 4BC
Bit number
31
Field name
SPGPSOFF_TOGGLE11
R/W
RW
Reset value
0
Sync pulse generator 11, 'Switch off' position
Bit 31
SPGPSOFF_TOGGLE11
toggle enable: 0b=disable, 1b=enable
Bit 30 - 16
SPGPSOFF_X11
X scan position
Bit 15
Reserved
Do not modify
Bit 14 - 0
SPGPSOFF_Y11
Y scan position
DIR_SPG11MaskOff
Register address
BaseAddress + 4C0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Bit 30 - 0
SPGMKOFF11
Mask bits: 0b=include bit in position matching, 1b= do not include this bit in position matching
DIR_SSqCycle
Register address
BaseAddress + 4C4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Bit 5 - 0
SSQCYCLE
Sequencer cycle length (number -1) of sequencer cycles
22-16
H
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPGPSON_X11
H
H
H
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPGPSOFF_X11
H
H
H
0
H
15
Reserved
RW
RW
0
0
H
H
SPGMKON11
RW
0
H
15
Reserved
RW
RW
0
0
H
H
SPGMKOFF11
RW
0
H
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPGPSON_Y11
RW
0
H
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPGPSOFF_Y11
RW
0
H
SSQCYCLE
RW
0
H
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