Dmac Source Address Register (Dmacsax) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

15.6.5 DMAC source address register (DMACSAx)

ch0：FFFD_0000+18 (h) ch1：FFFD_0000+28 (h) ch2：FFFD_0000+38 (h)
Address
ch4：FFFD_0000+58 (h) ch5：FFFD_0000+68 (h) ch6：FFFD_0000+78 (h)
Bit 31 30 29
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0
Bit 15 14 13
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0
Bit field
No. Name
31-0 DMACSA[31:0] These bits are used to specify source address to start DMA transfer, and they are able to
(DMAC Source be read during DMA transfer.
Address) When fixed address function (DMACB/FS) is disabled, these bits are incremented
according to the transfer width (DMACB/TB) after completing source address properly.
After the DMA transfer, DMAC sets the next source address to these bits.
[Note]
It is prohibited to set DMAC register address to DMACSA.
15-14
FFFD_0000+48 (h)
FFFD_0000+88 (h)
28 27 26 25
0 0 0 0
12 11 10 9
0 0 0 0
DMACSA
x(h) Source address to start DMA transfer
(Initial value: 32'h00000000)
24 23 22 21
DMACSA[31:16]
0 0 0 0
8 7 6 5
DMACSA[15:0]
0 0 0 0
Description
Function
ch3：
ch7：
20 19 18 17
0 0 0 0
4 3 2 1
0 0 0 0
16
0
0
0