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MB86R02 'Jade-D' Hardware Manual V1.64
9.5.5 ICR monitoring register (ICRMN)
The ICRMN register displays the interrupt level of a current IRQ interrupt source.
1111
is displayed if the IRQ interrupt source is not larger than the set value of this register. Moreover,
B
the interrupt source at the highest level is displayed if the IRQ interrupt transmission source is larger
than the set value of this register.
When the IRQF bit of the IRQF register is set to "1", the ICRMN register is updated. The displayed
interrupt level is not changed until the IRQF bit is cleared.
Moreover, the interrupt level is decided again after the IRQF bit is cleared, and the display is updated
by the source that sets the IRQF bit. When the IRQF bit is not made "1", the register value is not
defined.
Address
FFFF_FE00
Bit
31
30
29
Name
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
Bit
15
14
13
Name
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
Bit field
Number
Name
31-4
-
3-0
ILM3-0
9-18
IRC0:
or FFFE_8000
+ 0C
H
H
H
28
27
26
25
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
12
11
10
9
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
It is an unused bit.
The write access is ignored. The read value of these bits is undefined.
The interrupt source at the highest level is displayed when the IRQ interrupt source is larger
than the set value of the ILM register.
The initial value of these bits is undefined.
IRC1: FFFB_0000
IRC2: FFFB_1000
24
23
22
21
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
8
7
6
5
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
Explanation
+ 0C
H
H
+ 0C
H
H
20
19
18
17
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
4
3
2
1
-
ICRMN3 ICRMN2 ICRMN1 ICRMN0
R/W
R/W
R/W
R/W
X
X
X
X
16
-
R/W
X
0
R/W
X
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