Fujitsu MB86R02 Jade-D Hardware Manual page 289

MB86R02 'Jade-D' Hardware Manual V1.64
Restrictions
When DMA transfer is performed by external (DREQ) or peripheral (IDREQ) requests, there are
some restrictions for the external and peripheral signal pins.
6. DREQ/IDREQ
DREQ/IDREQ must remain asserted until DACK/IDACK are asserted. After they have been
asserted, DREQ/IDREQ must be negated within AHB clock (HCLK) cycles of "source access
cycle + destination access cycle – 1".
If the negation timing of DREQ/IDREQ violates the restrictions, the DMAC could start the
next transfer operation.
After completing 1 DMATE transfer and DACK/IDACK are asserted, the DMAC is able to
receive new transfer requests (DREQ/IDREQ level) for the next DMA transfers after the
negating period described above.
7. DACK/IDACK
After the DMAC has transferred the control signal to the source address, DACK/IDACK are
asserted for 1 cycle of the AHB clock (HCLK). In demand transfer mode, these signals
indicate that the DMAC is receiving a demand transfer request.
8. DEOP/IDEOP
Basically, DEOP/IDEOP are asserted for 1 AHB clock (HCLK) cycle when DMAC ends DMA
transfer properly or abnormally. Abnormal DMA transfer includes following cases:
• Forced termination by DSTP/IDSTP
• Forced termination by setting 1'b0 to DMACA/EB
• Receiving error response from source/destination
DSTP/IDSTP are used to forcibly terminate DMA transfer. Asserting them during DMA
transfer is permissible (it is also permissible to assert DSTP/IDSTP while DMA is not
transferring due to a transfer gap or interrupt function).
If these signals are used to forcibly terminate DMA transfer, they are not asserted until
DEOP/IDEOP have been asserted.
9. DEOP/IDEOP exception operation
If DSTP/IDSTP are asserted immediately after DREQ/DSTP have been asserted, the DMAC
may request the bus to execute an IDLE transfer. In this case, the DMAC may assert
DEOP/IDEOP for 2 or more AHB clock (HCLK) cycles.
The DEOP/IDEOP assertion period depends on the number of previous master transfer
cycles. Figure 15-6 shows example of this exception operation.
15-26