Fujitsu MB86R02 Jade-D Hardware Manual page 744

MB86R02 'Jade-D' Hardware Manual V1.64
Bit field
No. Name
24 TXFIM This is transmission FIFO interrupt mask bit.
It becomes "1" by software reset.
23-22 (Reserved) Reserved bits.
The write access is ignored. The read value of these bits is always "0".
21 RBERM This is interrupt mask bit of reception channel block size error.
It becomes "1" by software reset.
20 RXUDM This is reception underflow interrupt mask bit.
It becomes "1" by software reset.
19 RXOVM This is interrupt mask bit of reception FIFO overflow.
It becomes "1" by software reset.
18 EOPM This is interrupt mask bit by EOPI of STATUS register.
It becomes "1" by software reset.
17 RXFDM This is reception DMA request mask bit.
It becomes "1" by software reset.
16 RXFIM This is reception FIFO interrupt mask bit.
It becomes "1" by software reset.
15-12 (Reserved) Reserved bits.
The write access is ignored. The read value of these bits is always "0".
11-8 TFTH[3:0] Threshold value of transmission FIFO is set.
Empty space of transmission FIFO is threshold value or more and TXFIM is "0": Interrupt to
CPU occurs
Empty space of transmission FIFO is threshold value or more and TXFDM is "0": DMA is
requested to DMAC
TFTH is set according to the following expressions.
TFTH = Transmission FIFO threshold – 1
0 Interrupt to CPU by TXFI of STATUS register is not masked
1 Interrupt to CPU by TXFI of STATUS register is masked
0 Interrupt to CPU by RBERR of STATUS register is not masked
1 Interrupt to CPU by RBERR of STATUS register is masked
0 Interrupt to CPU by RXUDR of STATUS register is not masked
1 Interrupt to CPU by RXUDR of STATUS register is masked
0 Interrupt to CPU by RXOVR of STATUS register is not masked
1 Interrupt to CPU by RXOVR of STATUS register is masked
0 Interrupt to CPU by EOPI of STATUS register is not masked
1 Interrupt to CPU by EOPI of STATUS register is masked
0 DMA transfer is requested when reception data written to reception FIFO is
threshold value or more
1 DMA transfer is not requested though reception data written to reception
FIFO is threshold value or more
0 Interrupt to CPU by RXFI of STATUS register is not masked
1 Interrupt to CPU by RXFI of STATUS register is masked
Description
27-17