Fujitsu MB86R02 Jade-D Hardware Manual page 669

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MB86R02 'Jade-D' Hardware Manual V1.64
appropriate output signal. The length of the sequence as well as the contents of the RAM, consisting
of the position and the assigned output value are programmable.
Figure 22-6 Matching whole sequences with the Sync Sequencer
Operation is as follows. To start, the address counter is reset to zero and the RAM outputs the first
position that matches and the output value for this position. If the comparator signals match, the RAM
address is incremented, the preset output value (bit 31) is propagated and the RAM then outputs the
next position to match.
This match/address increment cycle continues until the programmed sequence length is reached. If
the last position is matched, the address counter is reset to zero again and the cycle starts again. It is
thus possible to generate arbitrarily complex waveforms with up to 64 edges (which is the maximum
sequence length).
22.5.2.4.5
Combining First Stage Sync Signals
As shown above, there are twelve sync pulse generator outputs and one sync sequencer output. To
obtain more complex waveforms, these signals can be combined in a second stage. Here, an array of
twelve sync mixers (SMx) is used to calculate Boolean functions of first-stage signals. Each sync
mixer can form any Boolean function on up to five inputs. The basic structure of one such mixer is
depicted in the following diagram.
22-35

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