Fujitsu MB86R02 Jade-D Hardware Manual page 261

MB86R02 'Jade-D' Hardware Manual V1.64
In order to calibrate DRVPx (x=1..4), decrease the value from 0xf to 0x0 until the DQX[0] bit is "1";
see Table 13-3 and Table 13-4. All DRVPx (x=1..4) must have the same value.
In order to calibrate DRVNx (x=1..4), increase the value from 0x0 to 0xf until the DQX[0] bit is "0"; see
Table 13-5 and Table 13-6. All DRVNx (x=1..4) must have the same value.
Table 13-3 Correspondence table of DRVP1/2 and DRIMR1/3/4 registers
DROISR1 register
11-8 DRVP2
3-0 DRVP1
Table 13-4 Correspondence table of DRVP3/4 and DRIMR2/3/4 registers
DROISR1 register
11-8 DRVP4
3-0 DRVP3
Table 13-5 Correspondence table of DRVN1/2 and DRIMR1/3/4 registers
DROISR2 register
15-12 DRVN2
7-4 DRVN1
Table 13-6 Correspondence table of DRVN3/4 and DRIMR2/3/4 registers
DROISR2 register
15-12 DRVN4
7-4 DRVN3
13-34
DRIMR1 register
15-8 DQX[15:8]
7-0 DQX[7:0]
DRIMR2 register
15-8 DQX[31:24]
7-0 DQX[23:16]
DRIMR1 register
15-8 DQX[15:8]
7-0 DQX[7:0]
DRIMR2 register
15-8 DQX[31:24]
7-0 DQX[23:16]
DRIMR3 register
1 DQSX[1]
0 DQSX[0]
DRIMR3 register
3 DQSX[3]
2 DQSX[2]
DRIMR3 register
1 DQSX[1]
0 DQSX[0]
DRIMR3 register
3 DQSX[3]
2 DQSX[2]
DRIMR4 register
1 DMX[1]
0 DMX[0]
DRIMR4 register
3 DMX[3]
2 DMX[2]
DRIMR4 register
1 DMX[1]
0 DMX[0]
DRIMR4 register
3 DMX[3]
2 DMX[2]