Register List - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
24.6 Register
This section describes the GPIO registers in detail.

24.6.1 Register list

Table 13-1 shows a summary of the GPIO registers.
Table 24-1 GPIO register list
Address
Base Offset
FFFE_9000 + 00 Port data register 0
H H
+ 04 Port data register 1
H
+ 08 Port data register 2
H
+ 0C (Reserved)
H
+ 10 Data direction register
H
0
+ 14 Data direction register
H
1
+ 18 Data direction register
H
2
+ 1C – (Reserved)
H
+ FFF
H
Abbreviatio
Register
n
GPDR0
GPDR1
GPDR2
–
GPDDR0
GPDDR1
GPDDR2
–
Description
Setting of input/output data of GPIO_PD[7:0] pin
Setting of input/output data of GPIO_PD[15:8] pin
Setting of input/output data of GPIO_PD[23:16] pin
Reserved area (access prohibited)
Control of input/output direction of GPIO_PD[7:0] pin
Control of input/output direction of GPIO_PD[15:8]
pin
Control of input/output direction of GPIO_PD[23:16]
pin
Reserved area (access prohibited)
24-3