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MB86R02 'Jade-D' Hardware Manual V1.64
10.5.2 External interrupt enable register (EIENB)
This register is to control masking external interrupt request output.
Address
Bit
31
30
29
Name
–
–
–
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
X
X
X
Bit
15
14
13
Name
–
–
–
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
X
X
X
Bit field
No.
Name
31-8
–
7-4
–
3-0
ENB3-0
FFFE_4000
28
27
26
25
–
–
–
–
X
X
X
X
12
11
10
9
–
–
–
–
X
X
X
X
Unused bit.
Write access is ignored. Read value of these bits is undefined.
Unused bit.
Write access is ignored. Read value of these bits is always "0".
Masking external interrupt request output is controlled.
0
External interrupt request is disabled
1
External interrupt request is enabled.
The interrupt request output corresponding to the bit written "1" is permitted (ENB0
controls INT_A[0] permission), and the request is output to interrupt controller (IRC0.)
Although the pin corresponding to the bit written "0" maintains interrupt factor, interrupt
is not requested to the controller.
These bits are initialized to "0000
+ 00
H
H
24
23
22
21
–
–
–
–
X
X
X
X
8
7
6
5
–
–
–
–
R0
R0
R0
R0
X
0
0
0
Description
" by reset.
B
20
19
18
17
–
–
–
–
X
X
X
X
4
3
2
1
ENB
ENB
ENB
–
ENB0
3
2
1
R/W R/W R/W R/W
0
0
0
0
10-5
16
–
X
0
0
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