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MB86R02 'Jade-D' Hardware Manual V1.64
24.6.3 Data direction register 0-2 (GPDDR0-2)
GPDDR0 - 2 registers are to control input/output directions of GPIO port, and their corresponding
GPIO pin is as follows.
• GPDDR0: GPIO bit 7 - 0 (GPIO_PD[7:0] pin)
• GPDDR1: GPIO bit 15 - 8 (GPIO_PD[15:8] pin)
• GPDDR2: GPIO bit 23 - 16 (GPIO_PD[23:16] pin)
Address
Bit
31
30
29
Name
R/W
–
–
Initial value
X
X
X
Bit
15
14
13
Name
R/W
–
–
Initial value
X
X
X
Bit field
No.
Name
31-8
(Reserved)
7-0
DDR0_7-0
GPDDR0: FFFE_9000
GPDDR1: FFFE_9000
GPDDR2: FFFE_9000
28
27
26
25
–
–
–
–
X
X
X
X
12
11
10
(Reserved)
–
–
–
–
X
X
X
X
Reserved bits.
Write access is ignored. Read value of these bits is undefined.
GPDR0 register's bit field.
This register controls input/output directions of GPIO_PD[7:0] pin.
0 GPIO acts as an input port
1 GPIO acts as an output port
GPIO pin corresponding to this register is as follows:
•
DDR0_7: GPIO_PD[7] pin
•
DDR0_6: GPIO_PD[6] pin
•
DDR0_5: GPIO_PD[5] pin
•
DDR0_4: GPIO_PD[4] pin
•
DDR0_3: GPIO_PD[3] pin
•
DDR0_2: GPIO_PD[2] pin
•
DDR0_1: GPIO_PD[1] pin
•
DDR0_0: GPIO_PD[0] pin
These bits are initialized to "0" by reset.
+ 10
H
H
+ 14
H
H
+ 18
H
H
24
23
22
21
(Reserved)
–
–
–
–
X
X
X
X
9
8
7
6
DDR0_7
DDR0_6
DDR0_5
DDR1_1
DDR1_1
DDR1_1
5
4
DDR2_2
DDR2_2
DDR2_2
3
2
–
–
R/W R/W R/W R/W R/W R/W R/W R/W
X
0
0
Description
20
19
18
17
–
–
–
–
X
X
X
5
4
3
2
DDR0_4
DDR0_3
DDR0_2
DDR0_1
DDR1_1
DDR1_1
DDR1_1
DDR1_9
3
2
1
0
DDR2_1
DDR2_2
DDR2_1
DDR2_1
1
0
9
8
0
0
0
0
16
–
–
X
X
1
0
DDR0_0
DDR1_8
DDR2_1
7
6
0
0
24-7
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