Global Address; Register Summary - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
Register address
Register address shows the address (Offset address) of the register.
Bit number
Bit number shows bit position of the register.
Field name
Field name shows bit name of the register.
R/W
R/W shows the read/write attribute of each bit field:
•
R: Read
•
W: Write
•
W1C: Writing a value of "1" clears the register.
Reset value
Reset value indicates the value of each bit field immediately after reset.
•
0: Initial value is "0".
•
1: Initial value is "1".
•
X: Undefined.
Unused register fields are marked with a solid grey background.
Bit vectors are unsigned integers, if nothing else specified.
23.6.2

Global Address

For the module base address, please refer to the global address map of this manual.
23.6.3

Register Summary

Address Register Name
Base address + 0
H
Base address + 4
H
Base address + 8
H
Base address + C
H
Base address +
10
H
Base address +
14
H
Base address +
18
H
Base address +
1C
H
Base address +
20
H
Base address +
24
H
Base address +
28
H
Base address +
2C
H
Base address +
30
H
Base address +
34
H
Base address +
38
H
SWReset SW reset
RldCfg general configuration register
StrideCfg0 Stride general configuration register
StrideCfg1 Line / Stride Length
BYTECNT Target number of decompressed bytes
OFIFO Output FIFO Control
DestAddress Local AHB-master transfer Destination address
AHBMCtrl Local AHB-master transfer Configuration/Control
RLDCtrl General Control
IEN Interrupt Enable register
Interrupt status flags, a '1' signifies that the
ISTS corresponding interrupt condition occurred (even if
interrupt is disabled), write '1' clears the flag,
Status Status register
SAHBData AHB Slave Input Data
TransferCount Local AHB-master transfer count
CurAddress Local AHB-master transfer Current address
Description
23-5