Fujitsu MB86R02 Jade-D Hardware Manual page 342

MB86R02 'Jade-D' Hardware Manual V1.64
Bit init Name
: ial
cfg_ddown_enable
7 0
cfg_sbdown_smode
6 0
cfg_clk_core1_enable
5 1
cfg_clk_core2_enable
4 0
reserved
3 0
reserved
2 1
reserved
1 0
reserved
0 0
Table 17-2 TX Config_byte_5
Bit init Name
ial
reserved
7 0
reserved
6
0
config_byte_5
Description
APIX PHY (Soft IP) / Ashell: configure
downstream data path
0: disable data mode / enable pixel stream
mode
1: enable data mode / disable pixel stream
mode
Note:
for proper operation the following settings
are mandatory
cfg_pxdata_width[1:0] := '00'
cfg_px_in_ctrl_piggyback[1:0] := '00'
APIX PHY (Soft IP): relation of downstream
sideband data to core clock of APIX PHY
0: asynchronous (sb data are 2-stage
registered internal, have to be used with
external AShell)
1: synchronous (have to be used with
internal AShell)
APIX PHY (Soft IP)
1: enable core clock of APIX PHY
0: disable
APIX PHY (Soft IP)
1: enable core clock of Ashell
0: disable
do not change
do not change
do not change
do not change
config_byte_6
Description
do not change
do not change
17-29