Fujitsu MB86R02 Jade-D Hardware Manual page 94

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MB86R02 'Jade-D' Hardware Manual V1.64

The CRG unit supports 'clock gear' functionality (clock subdivision) with a clock enable signal.

Standby mode (standby and stop)

The ARM9 core and the CRG module support the following standby modes:

(1) Standby mode

The ARM926EJ-S core supports a standby mode that is called "Interrupt waiting

mode" with CP15. The STANDBYWFI signal is asserted and the internal clock

gate is closed so that it does not supply an input clock to submodules in standby

mode (refer to ARM926EJ-S technical reference manual, "12.1.1 dynamic

power management (interrupt mode waiting)".)

This CRG module does not have a function to stop the ARMCLK signal in

standby mode.

(2) STOP mode

When the STANDBYWFI (ARM926EJ-S) signal is set to "1" when STOPEN = 1,

the state changes to STOP mode through the standby mode (if STOPEN = 1,

this module's STANDBYWFI signal is "1".)

In this mode, the CRG stops all clocks and the PLL oscillator. Also, the stop

mode is released with an external rest or external interrupt.

The figure shows the STOP mode operation.

When the state is changed to the STOP mode, "1" should be written to the

PLLBYPASS bit of the PLL control register (CRPR).

Although the PLL proceeds with the oscillation stabilization waiting period when

STOP mode is released, the clock is not switched to PLL clock until the

Figure 5-11 Clock gear

Figure 5-12 STANDBYWFI mode (ARM926EJ-S)

Internal clock