Timing Chart - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
DREQ
DACK
DEOP
DSTP
HCLK
HBUSREQM (HDMAC)
HGRANTM (HDMAC)
HMASTER
Control
HREADY
HRESP
Figure 15-2 Example of DEOP/IDEOP exception operation
DREQ/IDREQ, DACK/IDACK, DEOP/IDEOP, and DSTP/IDSTP are not valid when DMA transfer
is performed in software request mode.

Timing chart

Figure 15-3 shows a block transfer as a timing chart.
15-18
Other master
NONSEQ or SEQ READ or WRITE
HDMAC Other master
IDLE NONSEQ or SEQ
OK
READ or WRITE