Related Manuals for Fujitsu MB86R02 Jade-D
Summary of Contents for Fujitsu MB86R02 Jade-D
- Page 1 Application Note MB86R02 ‘Jade-D’ EMI Optimization using SSCG © Fujitsu Microelectronics Europe GmbH Version 1.30...
- Page 2 1 year from the date of receipt by the customer. Should a Product turn out to be defect, Fujitsu Microelectronics GmbH’s entire liability and the customer’s exclusive remedy shall be, at Fujitsu Microelectronics GmbH’s sole discretion,...
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Page 3: Table Of Contents
Table of Contents Document Revision History....................4 Spread-Spectrum Clocking Introduction ................5 Clock Tree Overview......................6 Clock Signals that can be modulated.................7 The SSCG unit in MB86R02 'Jade-D' ................8 Operating Frequency Ranges...................8 Modulation Parameters.....................8 5.2.1 Modulation Period ......................8 5.2.2 Modulation Period Delta (Jitter) ..................9 5.2.3 Modulation Type ........................ -
Page 4: Document Revision History
1 Document Revision History Version Date Editor Comment 1.00 23.06.2009 Andy von Treuberg First draft version 1.10 15.01.2010 Andy von Treuberg Updated Figure 6 (Modulation Peak). Section 5.2.5 Modulation Shape: text and diagrams updated. SSCG_OFFSET: Should be left at default 0x0. Changes accordingly. Section 7.2 Added: table for recommended 20 kHz (SSCG_PERIOD) 1.20 19.01.2010... -
Page 5: Spread-Spectrum Clocking Introduction
2 Spread-Spectrum Clocking Introduction Spread-spectrum clocking has become more popular in portable electronics devices because of faster clock speeds and the increasing integration of high-resolution LCD displays in smaller and smaller devices. As these devices are designed to be lightweight and inexpensive, passive EMI reduction measures such as capacitors or metal shielding are not a viable option. -
Page 6: Clock Tree Overview
3 Clock Tree Overview Figure 3-1 Overview of Clock Structure PLL's Version 1.30... -
Page 7: Clock Signals That Can Be Modulated
4 Clock Signals that can be modulated The Hardware manual of MB86R02 'Jade-D' describes which clock signals can be modulated, some depending on the settings in the CSEl register (which control the multiplexers SELM and SELMCCLK). The table below serves as a reference, please refer to the latest Hardware Manual to be sure you have the most current information. -
Page 8: The Sscg Unit In Mb86R02 'Jade-D
5 The SSCG unit in MB86R02 'Jade-D' The SSCG unit plays an essential role in the MB86R02 'Jade-D' GDC providing the 'heartbeat' of the digital units in the device. Whereas the internal PLL provides a non-modulated clock to the internal units via the Clock/Reset Distribution unit, the SSCG can be configured and then activated to provide a modulated clock signal. -
Page 9: Modulation Period Delta (Jitter)
5.2.2 Modulation Period Delta (Jitter) The 'Modulation Period Delta' is the amount by which the period of the modulated output signal is intentionally 'jittered', i.e. alternately shifted up and down in the frequency spectrum. Figure 3 Modulation Period Jitter 5.2.3 Modulation Type The term 'Modulation Type' refers to the direction in which the frequency spectrum of the modulated output signal is spread. - Page 10 Figure 4 Modulation Types Version 1.30...
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Page 11: Modulation Peak
5.2.4 Modulation Peak The Modulation Peak (set using the SSCG_PEAK_FREQUENCY register) has two settings: SSCG_PEAK_FREQUENCY = 0 Varies the Modulation Peak from 0 to ±1.56% (recommended value due to the latency of internal calculations) SSCG_PEAK_FREQUENCY = 1 Varies the Modulation Peak from 0 to ±(2x 1.56%) Do not use this setting in a productive system, as it is primarily intended for testing and validation purposes only! For signal stability reasons, the 'Modulation Peak', i.e. -
Page 12: Modulation Shape
5.2.5 Modulation Shape The 'Modulation Shape' is the form of signal which is used to modulate the main output clock signal. There are two shapes: 'Triangle' and 'Dual Triangle'. 'Triangle' provides a first-stage EMI improvement (SSCG_PERIOD_JITTER = 0). The 'Dual Triangle' mode (SSCG_PERIOD_JITTER = any other value than 0) provides second-stage EMI improvement. -
Page 13: Using Frequency Offset (Sscg_Foffset)
5.3 Using Frequency Offset (SSCG_FOFFSET) Although it is possible to modify the SSCG_FOFFSET value in the range -1.56% to +1.56%, it is recommended that this setting is left at its default value of 0 (0x0). 6 Selecting the SSCG Operating Frequency This depends on the physical application (your design). -
Page 14: How To Configure The Sscg Unit
7 How to configure the SSCG Unit 7.1 SSCG Unit Default Values The SSCG unit has the following default settings: SSCG_PERIOD = 35 kHz. Note the recommended value for use is 20 kHz! SSCG_PERIOD_JITTER = 0x90. Note the recommended value for use is approx. 0x70! SSCG_CTRL.SSCG_TYPE = 0x11 (Centerspread) Modulation Peak = +/- 1.56% SSCG_FOFFSET = 0x0... -
Page 15: Calculating Sscg_Fstep
7.3 Calculating SSCG_FSTEP For informational purposes: − SSCG FREQUENCY OFFSET SSCG_FSTEP = SSCG PERIOD SSCG PERIOD JITTER Where A = Absolute value of Modulation Peak (e.g. 1.56), i.e. no +/- B = max_peak = 3.125 for SSCG_PEAK_FREQUENCY = 0 B = max_peak = 6.25 for SSCG_PEAK_FREQUENCY = 1 (do not use) k = 1 if SSCG_TYPE =3 (Centerspread) otherwise k = 2 Version 1.30... -
Page 16: Enabling The Sscg Unit
8 Enabling the SSCG Unit It is important to follow an specific scheme to enable the SSCG unit in order to avoid causing a spike on the clock signal of the effected clock domains. Note that the registers used in the following example description are in the CRG (Base Address: FFFE_7000) and the SSCG (Base Address: FFFE_7080) units! 1. -
Page 17: Disabling The Sscg Unit
11 Disabling the SSCG Unit It is important to follow an specific scheme to disable the SSCG unit in order to avoid causing a spike on the clock signal of the effected clock domains. Use the following programming sequence: (example). Note that the registers used in the following description are in the CRG (Base Address: FFFE_7000) and the SSCG (Base Address: FFFE_7080) units! 1.