Indirect Addressing; B.4 Indirect Addressing - Fujitsu F2MC-16LX Hardware Manual

APPENDIX
B.4

Indirect Addressing

In indirect addressing mode, an address is specified indirectly by the address data of
an operand.
I Indirect Addressing
❍ Register indirect addressing (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address.
Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used,
system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or
additional data bank register (ADB) when RW2 is used.
❍ Register indirect addressing with post increment (@RWj+ j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After
operand operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a
long word). Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or
RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is
used, or additional data bank register (ADB) when RW2 is used.
If the post increment results in the address of the register that specifies the increment, the
incremented value is referenced after that. In this case, if the next instruction is a write
instruction, priority is given to writing by an instruction and, therefore, the register that would be
incremented becomes write data.
524
Figure B.4-1 Example of register indirect addressing (@RWj j = 0 to 3)
(This instruction reads data by register indirect addressing and stores it in A.)
MOVW A, @RW1
Before execution
After execution
A 0 7 1 6 2 5 3 4
RW1 D 3 0 F DTB 7 8
A 2 5 3 4 F F E E
RW1 D 3 0 F DTB 7 8
Memory space
78D310H F F
78D30FH E E