Multi-Gigabit Transceivers; Xapp687: 64B/66B Encoder/Decoder; Xapp756: Transmitting Ddr Data Between Lvds And Rocketio Cml Devices; Xapp763: Local Clocking For Mgt Rxrecclk In Virtex-Ii Pro Devices - Xilinx RocketIO User Manual

Product Not Recommended for New Designs

Characterization Reports

This application note describes how to use the RocketIO multi-gigabit transceivers
available in the Virtex-II Pro family of FPGA devices to implement a transmitter that can
support both SD-SDI and HD-SDI. The flexibility of the RocketIO transceivers combined
with the programmable logic of the Virtex-II Pro devices makes it possible to implement
multi-rate SDI interfaces.
Since all Virtex-II Pro devices have four or more RocketIO transceivers, it is possible to
implement multiple HD-SDI and SDI-SDI interfaces in a single FPGA.
XAPP684: Multi-Rate HD/SD-SDI Receiver Using Virtex-II Pro RocketIO

Multi-Gigabit Transceivers

The SD-SDI standard is widely used in broadcast studios and video production centers to
transport standard definition (SD) digital video serially over video coax cable. The HD-SDI
standard is similar, but transports high-definition (HD) digital video. The SD-SDI and HD-
SDI standards are similar enough that it is possible to implement interfaces for video
equipment that support both standards through the same connector.
This application note describes how to use the RocketIO multi-gigabit transceivers
available in the Virtex-II Pro family of FPGA devices to implement a receiver that can
support both SD-SDI and HD-SDI. The flexibility of the RocketIO transceivers combined
with the programmable logic of the Virtex-II Pro devices makes it possible to implement
multi-rate SDI interfaces.

XAPP687: 64B/66B Encoder/Decoder

This application note describes the encoding and decoding blocks of the 64B/66B encoding
scheme. This application allows designs to use the RocketIO™ transceiver of the Virtex-II
Pro™ device or an external SerDes with either Virtex-II™ or Virtex-II Pro devices.
XAPP756: Transmitting DDR Data Between LVDS and RocketIO CML
Devices
The serial transfer of data between devices on a board or cards on a backplane using the
LVDS differential standard is well established. Existing cards need to be able to interface to
newer technologies. This application note discusses two possible ways to interconnect
standard LVDS transceivers with the Current Mode Logic (CML) technology used in Xilinx
RocketIO™ multi-gigabit transceivers (MGTs) through AC coupling and DC coupling.

XAPP763: Local Clocking for MGT RXRECCLK in Virtex-II Pro Devices

This application note describes the local clocking resources available in the Virtex-II Pro
architecture for the RXRECCLK of the 3.125 Gb/s RocketIO™ multi-gigabit transceivers
(MGTs). Using RXRECCLK with local clock routing can enable applications to bypass the
MGT's elastic buffer, thus reducing latency without consuming global clock resources.
Along with a reference design, this application note explains how to use the local clocking
resources.
Characterization Reports
Characterization Reports can be accessed from:
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=Reports.
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
www.xilinx.com
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