Gtx Tx Component-Level Resets - Xilinx Virtex-6 FPGA User Manual

Chapter 3: Transmitter
Notes relevant to
1.
2.
3.

GTX TX Component-Level Resets

GTX TX component resets are primarily used for special cases. These resets are needed
when only the reset of a specific subsection is required. Each of the component-level reset
signals is described in
All transmitter component resets are asynchronous.
resets and the components that they reset.
Table 3-9: Available Transmitter Resets and the Components Reset by Them
www.BDTIC.com/XILINX
140
Figure 3-11:
GTXTEST[1] is only required when the TX output clock divider,
TXPLL_DIVSEL_OUT, is set to /2 or /4.
The timing of the reset sequencer inside the GTX TX depends on the frequency of an
internal clock and certain configuration attributes. The estimate given in
assumes that the frequency of the internal clock is 50 MHz with default values for the
configuration attributes.
The entire GTX TX is affected by GTXTXRESET. If the RX PLL is supplying the clock
for the TX datapath, GTXTXRESET and GTXRXRESET must be tied together.
Table 4-52, page
Component
FPGA TX Interface
TX Gearbox
TX Buffer
8B/10B Encoder
TX PCS
TX Polarity
Pattern Generator
5x Oversampler
TX Delay Aligner
www.xilinx.com
261.
Table 3-9 summarizes the transmitter
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Figure 3-11
✓
✓
✓
✓
✓
✓
✓
✓