Pcists - Pci Status Register - Intel I7-900 DESKTOP PROCESSOR - DATASHEET VOLUME 2 Datasheet

2.5.8

PCISTS - PCI Status Register

The PCI Status register is a 16-bit status register that reports the occurrence of various
error events on this device's PCI interface.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
Bit
15
14
13
12
11
10:9
8
7
6
5
40
0
0-1
06h
2
0-1, 4-5
06h
3
0-2, 4
06h
4-6
0-3
06h
Reset
Type
Value
Detect Parity Error (DPE)
RO 0
The host bridge does not implement this bit and is hardwired to a 0.
Signaled System Error (SSE)
This bit is set to 1 when this device generates an SERR message over the bus
RO 0
for any enabled error condition. If the host bridge does not signal errors using
this bit, this bit is hardwired to a 0 and is read only.
Received Master Abort Status (RMAS)
This bit is set when this device generates request that receives an Unsupported
RO 0
Request completion packet. Software clears the bit by writing 1 to it.
If this device does not receive Unsupported Request completion packets, the bit
is hardwired to 0 and is read only.
Received Target Abort Status (RTAS)
This bit is set when this device generates a request that receives a Completer
RO 0
Abort completion packet. Software clears this bit by writing a 1 to it.
If this device does not receive Completer Abort completion packets, this bit is
hardwired to 0 and read only.
Signaled Target Abort Status (STAS)
RO 0
This device will not generate a Target Abort completion or Special Cycle. This bit
is not implemented in this device and is hardwired to a 0.
DEVSEL Timing (DEVT)
These bits are hardwired to 00. This device does not physically connect to PCI
RO 0
bus X. These bits are set to "00" (fast decode) so that optimum DEVSEL timing
for PCI bus X is not limited by this device.
Master Data Parity Error Detected (DPD)
RO 0
PERR signaling and messaging are not implemented by this bridge, therefore
this bit is hardwired to 0.
Fast Back-to-Back (FB2B)
This bit is hardwired to 1. This device is not physically connected to a PCI bus.
RO 1
This bit is set to 1 (indicating back-to-back capabilities) so that the optimum
setting for this PCI bus is not limited by this device.
RO 0
Reserved
66 MHz Capable
RO 0
Does not apply to PCI Express. Hardwired to 0.
Register Description
Description
Datasheet