Mchbar Registers In Memory Controller - Common; Mad_Chnl-Address Decoder Channel Configuration Register; Mchbar Registers In Memory Controller - Common Register Address Map - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.16 MCHBAR Registers in Memory Controller –
Common
Table 2-18
the sections following the table.
Table 2-18. MCHBAR Registers in Memory Controller – Common Register Address Map
Address
Offset
0–4FFFh
5000–5003h
5004–5007h
5008–500Bh
500C–505Fh
5060–5063h
5064–50FFh
2.16.1 MAD_CHNL—Address Decoder Channel Configuration
Register
This register defines which channel is assigned to be channel A, channel B, and channel
C according to the rule:
size(A)  size (B)  size(C)
Since the processor implements only two channels, channel C is always channel 2, and
its size is always 0.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:6
5:4
3:2
1:0
Datasheet, Volume 2
lists the registers arranged by address offset. Register bit descriptions are in
Register
Symbol
RSVD Reserved
MAD_CHNL Address decoder Channel Configuration
MAD_DIMM_ch0 Address Decode Channel 0
MAD_DIMM_ch1 Address Decode Channel 1
RSVD Reserved
PM_SREF_config Self Refresh Configuration
RSVD Reserved
0/0/0/MCHBAR_MCMAIN
5000–5003h
00000024h
RW-L
32 bits
0000000h
Reset RST/
Attr
Value PWR
RO 0h
RW-L 10b
RW-L 01b Uncore
RW-L 00b Uncore
Register Name
Description
Reserved
Reserved
Channel B assignment (CH_B)
CH_B defines the mid-size channel:
00 = Channel 0
01 = Channel 1
10 = Channel 2
Channel A assignment (CH_A)
CH_A defines the largest channel:
00 = Channel 0
01 = Channel 1
10 = Channel 2
Reset
Access
Value
0h RO
00000024h RW-L
00600000h RW-L
00600000h RW-L
— —
000100FFh RW-L
— —
209