Processor Status Register - Intel i86W Manual

REGISTERS
The control registers are accessible only by load and store control-register instructions;
the integer and floating-point registers are accessed by arithmetic operations and load
and store instructions. The special-purpose registers KR, KI, T, and MERGE are used
by a few specific instructions. For information about initialization of registers, refer to
the reset trap in Chapter 7. For information about protection as it applies to registers,
refer to the
st.e
instruction in Chapter 5.
3.1 INTEGER REGISTER FILE
There are 32 integer registers, each 32-bits wide, referred to as
rO
through
r31,
which are
used for address computation and scalar integer computations. Register
rO
always re-
turns zero when read, independently of what is stored in it. This special behaviour of
rO
makes it useful for modifying the function of certain instructions. For example, specify-
ing
rO
as the destination of a subtract (thereby effectively discarding the result) produces
a compare instruction. Similarly, using
rO
as one source operand of an OR instruction
produces a test-for-zero instruction.
3.2 FLOATING-POINT REGISTER FILE
There are 32 floating-point registers, each 32-bits wide, referred to as
fO
through
f31,
which are used for floating-point computations. Registers
fO
and
f1
always return zero
when read, independently of what is stored in them. The floating-point registers are also
used by a set of integer operations, primarily for graphics computations.
The floating-point registers act as buffer registers in vector computations, while the data
cache performs the role of the vector registers of a conventional vector processor.
When accessing 64-bit floating-point or integer values, the i860 microprocessor uses an
even/odd pair of registers. When accessing 128-bit values, it uses an aligned set of four
registers
(fO, f4, f8, ... , f28).
The instruction must designate the lowest register number
of the set of registers containing 64- or 128-bit values. Misaligned register numbers
produce undefined results. The register with the lowest number contains the least signif-
icarit part of the value.
3.3 PROCESSOR STATUS REGISTER
The processor status register
(psr)
contains miscellaneous state information for the cur-
rent process. Figure 3-2 shows the format of the
psr.
Fields marked by an asterisk in the
figure can be changed only in supervisor mode.
• BR (Break Read) and BW (Break Write) enable a data access trap when the operand
address matches the address in the db register and a read or write (respectively)
occurs. (Refer to section 3.5 for more about the db register.)
• Various instructions set CC (Condition Code) according to the value of the result, as
explained in Chapter 5. The conditional branch instructions test CC. The bla instruc-
tion described in Chapter 5 sets and tests LCC (Loop Condition Code).
3-2