Errsts - Error Status; Error Status Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

6.1.2

ERRSTS - Error Status

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register is used to report various error conditions via the SERR DMI messaging
mechanism. An SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers).
These bits are set regardless of whether or not the SERR is enabled and generated.
After the error processing is complete, the error logging mechanism can be unlocked by
clearing the appropriate status bit by software writing a '1' to it
Table 16. Error Status Register (Sheet 1 of 2)
Bit
15:13
12
11
10
9
8
7
6:2
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
72
Access Default
Value
RO 000b
RW1C-S 0b
RW1C-S 0b
RO 0b
RW1C-S 0b
RO 0b
RW1C-S 0b
RO 00h
®
Celeron
Processor Configuration Registers
0/0/0/PCI
C8-C9h
0000h
RO; RW1C-S;
16 bits
RST/
PWR
Core Reserved
Core Processor Software Generated Event for
SMI (GSGESMI):
This indicates the source of the SMI was a
Device 2 Software Event.
Core Processor Thermal Sensor Event for SMI/
SCI/SERR (GTSE):
Indicates that a Processor Thermal Sensor trip
has occurred and an SMI, SCI or SERR has
been generated. The status bit is set only if a
message is sent based on thermal event
enables in Error command, SMI command and
SCI command registers. A trip point can
generate one of SMI, SCI, or SERR interrupts
(two or more per event is illegal). Multiple trip
points can generate the same interrupt, if
software chooses this mode, subsequent trips
may be lost. If this bit is already set, then an
interrupt message will not be sent on a new
thermal sensor event
Core Reserved
Core LOCK to non-DRAM Memory Flag (LCKF):
When this bit is set to 1, the Processor has
detected a lock operation to memory space that
did not map into DRAM
Core Reserved
Core DRAM Throttle Flag (DTF):
1: Indicates that a DRAM Throttling
condition occurred.
0: Software has cleared this flag since the
most recent throttling event.
Core
Reserved
®
Processor P4500, P4505 Series
.
Description
April 2010
Document Number: 323178-002