Device 2 Io; Index-Mmio Address Register; Data-Mmio Data Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.9

Device 2 IO

Table 2-11. Device 2 IO Register Address Map
Address
Offset
0–3h
4–7h
2.9.1 INDEX—MMIO Address Register
A 32-bit I/O write to this port loads the offset of the MMIO register or offset into the
GTT that needs to be accessed. An I/O Read returns the current value of this register.
This mechanism to access internal graphics MMIO registers must not be used to access
VGA IO registers which are mapped through the MMIO space. VGA registers must be
accessed directly through the dedicated VGA IO ports.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:21
20:2
1:0
2.9.2 DATA—MMIO Data Register
A 32-bit I/O write to this port is re-directed to the MMIO register/GTT location pointed
to by the INDEX register. A 32 bit IO read to this port is re-directed to the MMIO
register/GTT location pointed to by the INDEX register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
31:0
140
Register
Symbol
Index MMIO Address Register
Data MMIO Data Register
0/2/0/PCI IO
0–3h
00000000h
RW
32 bits
00000000h
Reset RST/
Attr
Value PWR
RO 0h
FLR,
RW 00000h
Uncore
FLR,
RW 00b
Uncore
0/2/0/PCI IO
4–7h
00000000h
RW
32 bits
Reset RST/
Attr
Value PWR
FLR,
RW 00000000h
Uncore
Processor Configuration Registers
Register Name
Description
Reserved
Register/GTT Offset (REGGTTO)
This field selects any one of the DWORD registers within the MMIO
register space of Device 2 if the target is MMIO Registers.
This field selects a GTT offset if the target is the GTT.
Target (TARG)
00 = MMIO Registers
01 = GTT
1X = Reserved
Description
MMIO Data Window (DATA)
This field is the data field associated with the IO2MMIO access.
Reset
Access
Value
00000000h RW
00000000h RW
Datasheet, Volume 2