Rx Write Logic; Dbgrx Data Register - Intel PXA255 User Manual

Update_DR parallel loads DBG_SR[35:1] into DBG_REG[34:0]. Whether the new data gets
written to the RX register or an overflow condition is detected depends on the inputs to the RX
write logic.
10.10.6.1

RX Write Logic

The RX write logic
1) Enable the debugger write to RX - the logic ensures only new, valid data from the debugger
is written to RX. In particular, when the debugger polls TXRXCTRL[31] to see whether the
debug handler has read the previous data from RX. The JTAG state machine must go through
Update_DR, which should not modify RX.
2) Clear DBG_REG[34] - mainly to support high-speed download. During high-speed
download, the debugger continuously scans in data to send to the debug handler and sets
DBG_REG[34] to signal the data is valid. Since DBG_REG[34] is never cleared by the
debugger in this case, the '0' to '1' transition used to enable the debugger write to RX would
not occur.
3) Set TXRXCTRL[31] - When the debugger writes new data to RX, the logic automatically
sets TXRXCTRL[31], signalling to the debug handler that the data is valid.
4) Set the overflow flag (TXRXCTRL[30] - During high-speed download, the debugger does
not poll to see if the handler has read the previous data. If the debug handler stalls long
enough, the debugger may overwrite the previous data before the handler can read it. The logic
sets the overflow flag when the previous data has not been read yet, and the debugger has just
written new data to RX.
Figure 10-4. RX Write Logic
10.10.6.2

DBGRX Data Register

The bits in the DBGRX data register
processor. The data register also contains a bit to flush previously written data and a high-speed
download flag.
Intel® XScale™ Microarchitecture User's Manual
(Figure 10-4) serves 4 functions:
DBG_REG[34]
Latch
Latch
TXRXCTRL[31]
Core CLK
(Figure
Clear DBG_REG[34]
RX write enable
Set TXRXCTRL[31]
Set overflow flag
(TXRXCTRL[30])
10-5) are used by the debugger to send data to the
Software Debug
10-21