Ma - Message Address; Md - Message Data; Ma - Message Address Register; Md - Message Data Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

6.2.31

MA - Message Address

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Table 54.

MA - Message Address Register

Default
Bit Access
31:2 RW 00000000h
1:0 RO
6.2.32

MD - Message Data

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Table 55.

MD - Message Data Register

Default
Bit Access
Value
15:0 RW 0000h
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
110
RST/
Value PWR
Core Message Address (MA)
Used by system software to assign an MSI address to the
device. The device handles an MSI by writing the padded
contents of the MD register to this address.
00b Core Force DWord Align (FDWA)
hard wired to 0 so that addresses assigned by system software
are always aligned on a dword address boundary.
RST/
PWR
Core Message Data (MD)
Base message data pattern assigned by system software and
used to handle an MSI from the device.
When the device must generate an interrupt request, it writes a
32-bit value to the memory address specified in the MA register.
The upper 16 bits are always set to 0. The lower 16 bits are
supplied by this register.
®
Celeron
Processor Configuration Registers
0/6/0/PCI
94-97h
00000000h
RO; RW
32 bits
Description
0/6/0/PCI
98-99h
0000h
RW
16 bits
Description
®
Processor P4500, P4505 Series
April 2010
Document Number: 323178-002