Ddr2 Data/Dm/Ecc Byte Lane Topology; Ddr2 Data Strobe Routing (Dqs/Dqs#) Topology (One Strobe Per Byte Lane); B-29 Data And Strobe Signal Group Routing Guidelines - Intel EP80579 Manual

System Memory Interface (Memory Down)—Intel
Figure B-10. DDR2 Data/DM/ECC Byte Lane Topology
EP80579
Figure B-11. DDR2 Data Strobe Routing (DQS/DQS#) Topology (One Strobe per Byte Lane)
Table B-29. Data and Strobe Signal Group Routing Guidelines (Sheet 1 of 2)
Signal Group
Reference Plane
Characteristic Trace Impedance
(Zo)
Layer assignment
Nominal Trace Width
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Order Number: 320068-005US
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EP80579 Integrated Processor Product Line
L0
Pkg
Lp
=
Stripline Routing
=
Microstrip Routing
EP80579
L0
Pkg
Lp
=
Stripline/Microstrip Routing
=
Microstrip Routing
Parameter
Data & Data Mask
Data & Mask (DQ & DM)
Ground Referenced
Single Ended Impedance
• 50Ω ±10% for L1/L10 (Microstrip routing (e2e))
• 45Ω ±10% for L3/L5/L6/L8 (Stripline routing (e2e))
• Signals within the same Byte Lane must be routed on
See Stackup
Rsd
L1
L2
L2
L1
Routing Guidelines
Data Byte Lane
Byte Strobe (DQS/DQS#)
the same layer
L3 SDRAM
SDRAM
Rsd
L3
Figure
Strobe
May 2010
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