Mesi State Tables (82496 Cache Controller State Changes); Master 82496 Cache Controller Read Cycle - Intel 82496 CACHE CONTROLLER User Manual

COMPONENT OPERATION
3.7.4.
MESI State Tables (82496 Cache Controller State Changes)
Table 3-2. Master 82496 Cache Controller Read Cycle
Pres. Mem Bus CPU Bus
State Condition: Next State Activity Activity Comments
M !LOCK: M
-
!WT Normal Read Hit [M].
LOCK: M RTHR !KEN Read Through Cycle, Data From
Array.
E !LOCK: E
-
-
Normal Read Hit [E].
LOCK: E RTHR !KEN Read Through Cycle, Data From
Memory.
S
!LOCK.!TRO: S -
- Normal Read Hit lSI.
!LOCK.TRO.DAT: S !KEN Normal Read to Read-Only data
sector. Stays in [S] state, deacti-
vates
KEN# to disable caching in L 1
data cache.
!LOCK.TRO.!DAT: S
-
-
Normal Read to Read-Only code
sector. Stays in [S] state,
activates
KEN# to enable caching in L 1 code
cache.
LOCK: S RTHR !KEN Read Through Cycle, Data from
Memory.
I PCD+!MKEN+LOCK: I RNRM !KEN Non-Cacheable Read, Locked cy-
cles.
!PCD.MKEN.!LOCK.MRO.DAT: S LFIL !KEN Cacheable data read, Read-Only.
Fill line to 82496 Cache Controller
cache, but not to Pentium™
processor cache. Set the 82496
Cache Controller TRO bit.
!PCD.MKEN.!LOCK.MRO.!DAT: S LFIL Cacheable code read, Read-Only.
Fill line to 82496 Cache Controller
and Pentium processor caches. Set
the TRO bit in the 82496 Cache
Controller cache.
!PCD.MKEN.!LOCK.!MRO.(PWT + LFIL - Cacheable Reads, forced Write-
MWT):S Through.
!PCD.MKEN. !LOCK. !MRO. !PWT.
LFIL
-
Line not shared, thus enabling the
!MWT. !DRCTM: E 82496 Cache Controller to
move
into an exclusive state.
!PCD.MKEN. !LOCK. !MRO. !PWT. LFIL
-
As before with direct [M] state trans-
!MWT. DRCTM: M fer. Keep Pentium processor in
Write Through mode.
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