Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus - Intel 80960HA Datasheet

80960HA/HD/HT
Figure 35. Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus
PMCON
60
External
Function Ready
Burst
Control
Bit
29 28
Disabled Enabled
Value
0 1
NOTE:
Bits 31-30, 27-25, 13, and 5 are reserved.
A
CLKIN
ADS
A31:4, SUP,
CT3:0,D/C,
BE3:0, LOCK
W/R
BLAST
DT/R
DEN
A3:2
WAIT
D31:0,
DP3:0
PCHK
Pipe- Bus Parity
Odd
Lining Parity Enable
Width
24 23-22 21 20
OFF
32-Bit X Enabled
0
10 x 1
D
D
Valid
00 01
In1
In0
N
N N N
RDD
XDA WDD WAD
19-16 15-14 12-8 7-6
X X
0 0
xx xxxxx
0000
00
D D A
10 11
In2 In3
N
RAD
4-0
0
00000
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