Mode 32-Bit Read Transfer - Intel IXP28XX Manual

IXP28XX Network Processor
Slowport
7.1.2.2.4
Note: The IXP28XX CSR Receive Enable Register (SP_RXE) can be used to advance the data sampled
Figure 87.
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Read Transactions
As with the write operations, the read transactions to 16- and 32-bit devices will need to be
unpacked: eight bits per cycle prior to the data being sent back to the IXP28XX network processor
via the SP_AD bus. Again, the SP_CP, SP_OE_L, and SP_DIR signals implement the control logic
needed to perform the unpacking of the read data. This example also highlights the logic required
for Mode 3.
The glue logic is responsible for latching the 32-bit read data coming from the downstream device
on the rising edge of the read signal or as specified by the device.
Slowport interface signals presented to the glue logic during a read transaction.
internally before the rising edge of the SP_CLK. For programming SP_RXE, refer to the Intel®
IXP2400 and IXP2800 Network Processor Programmer's Reference Manual.
example of a Slowport Mode 3 Read with RXE = 2.

Mode 32-Bit Read Transfer

SP_ACK_L
28
SP_AD[7:0]
SP_ALE_L
SP_CLK
SP_CP
SP_CS_L[1:0]
SP_DIR
SP_OE_L
SP_RD_L
SP_WR_L
14 0
3 1
Figure 87 shows the timing of the
Figure 88 is an
0
3
Hardware Design Guide
B0601-01