Variable Latency Input/Output (Vlio) Interface - Intel PXA27 Series Design Manual

6.5.5

Variable Latency Input/Output (VLIO) Interface

When a companion chip is used as a variable latency I/O, its functionality is similar to that of an
SRAM. The chip is capable of inserting a variable number of wait states through the use of the
RDY pin. Use variable latency I/O in the memory space for any of the six static memory locations
(nCS<5:0>).
For variable latency I/O implementations, DQM<3:0> signals are used for the write byte enables,
where DQM<3> corresponds to the MSB in little endian mode. The PXA27x processor supplies 26
bits of byte address for access of up to 128 MBytes per chip select.
Variable latency I/O read accesses differ from SRAM read accesses in that the nOE toggles for
each beat of a burst. The first nOE assertion occurs two CLK_MEM cycles after the assertion of
the chip select, nCS<x>. For VLIO writes, nPWE is used instead of nWE so SDRAM refreshes is
executed while performing the VLIO transfers.
VLIO reads and writes differ from SRAM reads and writes. When the VLIO reads or writes, the
PXA27x processor starts sampling the data-ready input (RDY) on the rising edge of CLK_MEM in
two memory cycles. This is prior to the end of minimum nOE or nPWE assertion (MSCx[RDF]+1
memory cycles). The RDY signal is synchronized on input using a two-stage synchronizer, so
when the synchronized signal is high, the signal indicates that the I/O device is ready for data
transfer. RDY is tied high to cause a zero-wait-state I/O access. Read data is latched one memory
cycle after the third successful sample (on the rising edge). nOE or nPWE is de-asserted on the next
rising edge of CLK_MEM and the address changes on the subsequent rising edge of CLK_MEM.
Prior to a subsequent data beat, nOE or nPWE remains de-asserted for RDN+1 memory cycles.
The chip select and byte selects (DQM<3:0>) remain asserted for one memory cycle after the
burst's final nOE or nPWE de-assertion.
For both reads and writes to and from VLIO, a special DMA mode exists that causes the address to
not be increment to the VLIO. The special DMA mode allows port-type VLIO chips to interface to
the PXA27x processor. This is only valid VLIO memory. For more information, refer to the DMA
chapter in the Intel
For writes to VLIO, if all byte enables are turned off (masking out the data DQM = 0b1111), then
the write enable is suppressed (nPWE = 1) for this write beat to VLIO. Turning off all byte enables
causes a period when nCS is asserted, but neither nOE nor nPWE are asserted. This occurs when
there is a write of 1 beat to VLIO and all byte enables are turned off.
The memory controller indefinitely waits for assertion of the RDY signal. This hangs the system if
the external VLIO is not responding. System designers may want to consider a pull-up resistor on
the RDY signal to ensure this signal is high under all conditions except when the companion chip
drives this signal low to indicate the memory cycle needs extending.
®
Intel PXA27x Processor Design Guide
®
PXA27x Processor Family Developers Manual.
System Memory Interface
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