4.8
Memory Bus and PCMCIA AC Specifications
This section provides the timing information for these types of memory:
•
SRAM / ROM / Flash / Synchronous Fast Flash Asynchronous writes
ROM / Flash / Synchronous Fast Flash AC Specifications" on page
•
Variable latency I/O
page
•
Card interface (PCMCIA or Compact Flash)
Flash) AC Specifications" on page
•
Synchronous memories
page
Table 19. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications
Symbol
tromAS
tromAH
tromASW
tromAHW
tromCES
tromCEH
tromDS
tromDSWH MD(31:0), DQM(3:0) write data setup to nWE de-asserted
tromDH
tromNWE
Table 20. Variable Latency I/O Interface AC Specifications
Symbol
tvlioAS
tvlioASRW
tvlioAH
tvlioCES
tvlioCEH
tvlioDSW
tvlioDSWH
tvlioDHW
tvlioDHR
tvlioRDYH
tvlioNPWE
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
(Table 20, "Variable Latency I/O Interface AC Specifications" on
35)
(Table 22, "Synchronous Memory Interface AC Specifications 1" on
36)
MA(25:0) setup to nCS, nOE, nSDCAS (as nADV) asserted
MA(25:0) hold after nCS, nOE, nSDCAS (as nADV) de-
asserted
MA(25:0) setup to nWE asserted
MA(25:0) hold after nWE de-asserted
nCS setup to nWE asserted
nCS hold after nWE de-asserted
MD(31:0), DQM(3:0) write data setup to nWE asserted
MD(31:0), DQM(3:0) write data hold after nWE de-asserted
nWE high time between beats of write data
Description
MA(25:0) setubp to nCS asserted
MA(25:0) setup to nOE or nPWE asserted
MA(25:0) hold after nOE or nPWE de-asserted
nCS setup to nOE or nPWE asserted
nCS hold after nOE or nPWE de-asserted
MD(31:0), DQM(3:0) write data setup to nPWE asserted
MD(31:0), DQM(3:0) write data setup to nPWE de-
asserted
MD(31:0), DQM(3:0) hold after nPWE de-asserted
MD(31:0) read data hold after nOE de-asserted
RDY hold after nOE, nPWE de-asserted
nPWE, nOE high time between beats of write or read data
(Table 21, "Card Interface (PCMCIA or Compact
36)
Description
Electrical Specifications
(Table 19, "SRAM /
35)
MEMCLKs
1
1
3
1
2
1
1
2
1
2
MEMCLKs
1
1
1
2
1
1
2
1
0
0
2
35