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8XC196MC, MD, MH USER'S MANUAL
2.3.1
CPU Control
The CPU is controlled by the microcode engine, which instructs the RALU to perform operations
using bytes, words, or double-words from either the 256-byte lower register file or through a win-
dow that directly accesses the upper register file. (See Chapter 4, "Memory Partitions," for more
information about the register file and windowing.) CPU instructions move from the 4-byte
prefetch queue in the memory controller into the RALU's instruction register. The microcode en-
gine decodes the instructions and then generates the sequence of events that cause desired func-
tions to occur.
2.3.2
Register File
The register file is divided into an upper and a lower file. In the lower register file, the lowest 24
bytes are allocated to the CPU's special-function registers (SFRs) and the stack pointer, while the
remainder is available as general-purpose register RAM. The upper register file contains only
general-purpose register RAM. The register RAM can be accessed as bytes, words, or double-
words.
The RALU accesses the upper and lower register files differently. The lower register file is always
directly accessible with direct addressing (see "Addressing Modes" on page 3-5). The upper reg-
ister file is accessible with direct addressing only when windowing is enabled. Windowing is a
technique that maps blocks of the upper register file into a window in the lower register file. See
Chapter 4, "Memory Partitions," for more information about the register file and windowing.
2.3.3
Register Arithmetic-logic Unit (RALU)
The RALU contains the microcode engine, the 16-bit arithmetic logic unit (ALU), the master pro-
gram counter (PC), the processor status word (PSW), and several registers. The registers in the
RALU are the instruction register, a constants register, a bit-select register, a loop counter, and
three temporary registers (the upper-word, lower-word, and second-operand registers).
The PSW contains one bit (PSW.1) that globally enables or disables servicing of all maskable in-
terrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six
Boolean flags that reflect the state of your program. Appendix A, "Instruction Set Reference,"
provides a detailed description of the PSW.
All registers, except the 3-bit bit-select register and the 6-bit loop counter, are either 16 or 17 bits
(16 bits plus a sign extension). Some of these registers can reduce the ALU's workload by per-
forming simple operations.
2-4
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