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16.4.3 Selection of Oscillator Waiting Time after Exit from Software Standby Mode
Bits STS2 to STS0 in SYSCR should be set as follows.
Crystal Resonator: Set STS2 to STS0 so that the waiting time (for the clock to stabilize) is at
least 7 ms. Table 16-3 indicates the waiting times that are selected by STS2 to STS0 settings at
various system clock frequencies.
External Clock: Any value may be set.
Table 16-3 Clock Frequency and Waiting Time for Clock to Settle
Waiting
STS2 STS1
STS0
Time
0
0
0
8,192
states
0
0
1
16,384
states
0
1
0
32,768
states
0
1
1
65,536
states
1
0
—
131,072
states
1
1
—
: Recommended setting
16.4.4 Sample Application of Software Standby Mode
Figure 16-1 shows an example in which software standby mode is entered at the fall of NMI and
exited at the rise of NMI.
With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an
NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY
bit is set to 1; then the SLEEP instruction is executed to enter software standby mode.
Software standby mode is exited at the next rising edge of the NMI signal .
18MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz Unit
0.46
0.51
0.65
0.8
0.91
1.0
1.3
1.6
1.8
2.0
2.7
3.3
3.6
4.1
5.5
6.6
7.3
8.2
10.9
13.1
Illegal setting
1.0
1.3
2.0
4.1
2.0
2.7
4.1
8.2
4.1
5.5
8.2
16.4
8.2
10.9
16.4
32.8
16.4
21.8
32.8
65.5
ms
387
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