Dsp Core Response After Reactivation - Texas Instruments OMAP5910 Reference Manual

12.3.2.5 Interrupt Handling When the DSP Core Is Reactivated
Table 98. DSP Core Response After Reactivation
Interrupt
A maskable interrupt
DSP subsystem reset
12.3.2.6 Effect of a DSP Reset on the Idle Domains
12.3.2.7 DSP Module Idle Configuration Examples
SPRU890A
If the DSP core has been halted by an idle configuration, it can be reactivated
by a DSP subsystem reset or by a maskable interrupt that is enabled in an
interrupt enable register (IER0 or IER1). A maskable interrupt request will also
set the corresponding interrupt flag bit in an interrupt flag register (IFR0 or
IFR1). Table 98 summarizes how the DSP core responds after being
reactivated by maskable and nonmaskable interrupts. INTM is the global
interrupt mask bit in status register ST1_55.
Response After Reactivation
If INTM = 0:
The DSP core executes the interrupt service routine, executes the instruction
that follows the IDLE instruction, and continues from there. The interrupt flag bit
associated with the maskable interrupt will be cleared automatically when the
DSP core branches to the interrupt service routine.
If INTM = 1:
The DSP core executes the instruction that follows the IDLE instruction and then
continues from there. The interrupt service routine cannot be executed until
interrupts have been globally enabled through INTM. The interrupt flag bit
associated with the maskable interrupt will be set.
The DSP subsystem is reset. During a DSP subsystem reset, all idle domains
are made active.
After the DSP core is brought out of the idle state, the flag bit that was set in
the interrupt flag register (IFR0 or IFR1) has to be cleared before the DSP core
can be placed back in the idle state.
During a DSP subsystem reset, all idle domains are made active.
To put one or more domains in idle mode, set the corresponding bits in the ICR
register and then execute the DSP IDLE instruction. The idle status register
reflects the state of the DSP when the IDLE instruction is executed.
DSP Subsystem Reset, Clocking, Idle Control, and Boot
DSP Subsystem 223