Ti Peripheral Bus Bridges - Texas Instruments OMAP5910 Reference Manual

8

TI Peripheral Bus Bridges

8.1 Introduction
8.2 DSP Private Peripherals
SPRU890A
The TI peripheral bus (TIPB) bridges manage accesses to peripheral control
and data registers by the DSP core, DSP DMA controller, and MPU Interface
(MPUI) via two peripheral buses (see the DSP subsystem block diagram in
section 1.4):
DSP private peripheral bus. Peripherals connected here cannot be
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accessed by the MPU via the MPUI port.
DSP public peripheral bus. Peripherals connected here can be accessed
-
by the MPU via the MPUI port.
There are two TIPB bridges in the DSP subsystem:
The private TIPB bridge provides a preconfigured bus interface to
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peripherals residing on the DSP private peripherals bus.
The public TIPB bridge provides a user-configurable interface to
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peripherals on the DSP public peripheral bus. It includes functions to
configure the interface timing to the complement of peripherals operating
at a given time.
All peripheral control and data registers are located in the I/O space. To read
from or write to these registers, you must access the DSP subsystem I/O
space either through C language constructs or by using the assembly
language peripheral port register access qualifier. See the TMS320C55x DSP
Mnemonic Instruction Set Reference Guide (SPRU374) for more details.
Note:
Byte access to I/O space is not supported.
Peripherals on the DSP private peripheral bus are considered private
peripherals. The MPU cannot access these peripherals. DSP private
peripherals on OMAP5910 and OMAP5912 include:
Three timers
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Watchdog timer
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Interrupt handlers
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TI Peripheral Bus Bridges
DSP Subsystem 187