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3.9
EMAC Control Module Receive Threshold Interrupt Status Register
(CMRXTHRESHINTSTAT)
The receive threshold interrupt status register (CMRXTHRESHINTSTAT) is shown in
described in
Table
Figure 21. EMAC Control Module Receive Threshold Interrupt Status Register
31
15
Reserved
LEGEND: R = Read only; -n = value after reset
Table 18. EMAC Control Module Receive Threshold Interrupt Status Register
Bit
Field
31-8
Reserved
7-0
RXTHRESHINTTSTAT[n]
3.10 EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
The receive interrupt status register (CMRXINTSTAT) is shown in
Figure 22. EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
31
15
Reserved
LEGEND: R = Read only; -n = value after reset
Table 19. EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
Bit
Field
31-8
Reserved
7-0
RXPULSEINTTSTAT[n]
SPRUEQ6 – December 2007
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18.
(CMRXTHRESHINTSTAT)
R-0
(CMRXTHRESHINTSTAT) Field Descriptions
Value Description
0
Reserved
Receive threshold interrupt status. Each bit shows the status of the corresponding
channel n receive threshold interrupt.
Bit n = 0, channel n receive threshold interrupt is not pending.
Bit n = 1, channel n receive threshold interrupt is pending.
R-0
Field Descriptions
Value Description
0
Reserved
Receive interrupt status. Each bit shows the status of the corresponding channel n receive
interrupt.
Bit n = 0, channel n receive interrupt is not pending.
Bit n = 1, channel n receive interrupt is pending.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Reserved
R-0
8
7
RXTHRESHINTTSTAT
Figure
Reserved
R-0
8
7
RXPULSEINTTSTAT
EMAC Control Module Registers
Figure 21
and
R-0
22and described in
Table
R-0
16
0
19.
16
0
67