Idle Domains In The Dsp; Idle Control At The Dsp Subsystem Level - Texas Instruments OMAP5910 Reference Manual

12.3.1

Idle Control at the DSP Subsystem Level

12.3.2 Idle Control at the DSP Module Level
12.3.2.1 Idle Domains
Table 96. Idle Domains in the DSP
Domain Contents of the Domain
CPU DSP core and buses
DMA DSP DMA controller and DMA buses
SPRU890A
As mentioned in section 12.2, the main clock that feeds the DSP subsystem
is the DSP subsystem master clock (DSP_CK). DSP_CK feeds all the
modules included in the DSP module (a list of these modules is included in
section 1.2). The EN_DSPCK bit in the MPU Clock Control Prescaler Selection
Register (ARM_CKCTL) enables the DSP_CK (by default DSP_CK is
enabled).
To idle the DSP subsystem, follow these steps:
1) Place the DSP subsystem in reset by clearing the DSP_EN bit in the
Master Software Reset Register (ARM_RSTCT1).
2) Disable the DSP subsystem clock by clearing the EN_DSPCK bit in the
MPU Clock Control Prescaler Selection Register to (ARM_CKCTL).
For more information on the ARM_RSTCT1 and ARM_CKCTL registers, see
the OMAP5912 Multimedia Processor OMAP3.2 Subsystem Reference
Guide (SPRU749), or the OMAP5910 Dual-Core Processor Clock Generation
and System Reset Management Reference Guide (SPRU678).
The DSP module is divided into the idle domains described in this section. To
minimize power consumption, you can choose which domains are active and
which domains are idle at any given time. The current state of all domains is
collectively called the idle configuration.
The DSP is divided into the idle domains described in Table 96. You can control
which of these idle domains are active and which are idle at any given time,
as described in section 12.3.2.2.
DSP Subsystem Reset, Clocking, Idle Control, and Boot
Configurability
When the IDLE instruction is executed, the DSP core
remains active or becomes idle, depending on the chosen
idle configuration.
Regardless of this domain's state before a DSP
subsystem reset, it is active after a DSP subsystem reset.
When the IDLE instruction is executed, the DMA controller
remains active or becomes idle, depending on the chosen
idle configuration.
Regardless of this domain's state before a DSP
subsystem reset, it is active after a DSP subsystem reset.
DSP Subsystem 219