Figure 95.
MPUI Control Register (CTRL_REG)
31
15
Note:
R = Read, W = Write; −n = Value after reset; −x = Value after reset is not defined.
Table 90. MPUI Control Register (CTRL_REG) Field Descriptions
Bits
Field
31−23 Reserved
22−21 WORD SWAP
20−18 Reserved
17−16 BYTE SWAP
15−0
Reserved
SPRU890A
23
Value Description
These bits are not used.
These bits enable/disable word-swapping in the endianess conversion
logic of the MPUI.
00
Word-swap all accesses.
01
Word-swap only peripheral accesses.
10
Word-swap only memory accesses.
11
Disable word-swapping.
These bits are not used.
These bits enable/disable byte-swapping in the endianess conversion
logic of the MPUI.
00
Disable byte-swapping.
01
Byte-swap only peripheral accesses.
10
Byte-swap all accesses.
11
Byte-swap only memory accesses.
These bits are not used.
DSP Subsystem Endianess
22
21
20
WORD
SWAP
RW-0
DSP Subsystem
18
17
16
BYTE
SWAP
RW-3
0
203