Ifr0 And Ier0 Bit Locations (Omap5910) - Texas Instruments OMAP5910 Reference Manual

Table 91. OMAP5910 Level 1 Interrupt Mapping (Continued)
Hardware C55x DSP
Interrupt Core Vector
Priority
12
16
19
20
23
24
25 BERRIV (IV24)
26 DLOGIV (IV25)
27 RTOSIV (IV26)
28
29
30
31
32
†
NMI is not physically connected on OMAP devices, it is included here for compatibility with other C55x documentation.
Figure 98.

IFR0 and IER0 Bit Locations (OMAP5910)

15 14
DMAC5 DMAC4
RW-0 RW-0
7 6
GPIO SINT6
RW-0 RW-0
Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
SPRU890A
Vector
Address
Name (Byte Address)
IV18 IVPH:90h
IV19 IVPH:98h
IV20 IVPH:A0h
IV21 IVPH:A8h
IV22 IVPH:B0h
IV23 IVPH:B8h
IVPD:C0h
IVPD:C8h
IVPD:D0h
SIV27 IVPD:D8h
SIV28 IVPD:E0h
SIV29 IVPD:E8h
SIV30 IVPD:F0h
SIV31 IVPD:F8h
13 12
WDT UART3
RW-0 RW-0
5 4
MBX1 TCABORT
RW-0 RW-0
Name
DMAC0
MBX2 MPU-to-DSP mailbox #2
DMAC2
DMAC3
TIMER2 DSP private timer #2 interrupt
TIMER1 DSP private timer #1 interrupt
BERR
DLOG
RTOS
SINT27
SINT28
SINT29
SINT30
SINT31
11 10
SINT11 MPU
RW-0 RW-0
3 2
L2FIQ EMUINT
RW-0 RW-0
DSP Subsystem Interrupts
Interrupt Source
DSP DMA channel #0
interrupt
interrupt
DSP DMA channel #2
interrupt
DSP DMA channel #3
interrupt
Bus error interrupt
Data log interrupt
Real-time operating
system interrupt
Software interrupt #27
Software interrupt #28
Software interrupt #29
Software interrupt #30
Software interrupt #31
9 8
DMAC1 TIMER3
RW-0 RW-0
1 0
Reserved
R-0
DSP Subsystem 209