Dma Auxiliary Control Register; Dma Auxiliary Control Register Field Descriptions - Texas Instruments TMS320C6201 Reference Manual

Figure 5–12. DMA Auxiliary Control Register
31
Table 5–9. DMA Auxiliary Control Register Field Descriptions
Field
CH PRI
AUXPRI
Reserved
R, +0
Description
DMA channel priority
CH PRI = 0000b: fixed channel priority mode auxiliary channel highest priority
CH PRI = 0001b: fixed channel priority mode auxiliary channel 2nd-highest priority
CH PRI = 0010b: fixed channel priority mode auxiliary channel 3rd-highest priority
CH PRI = 0011b: fixed channel priority mode auxiliary channel 4th-highest priority
CH PRI = 0100b: fixed channel priority mode auxiliary channel lowest priority
CH PRI = other, reserved
Auxiliary channel priority mode
AUXPRI = 0: CPU priority
AUXPRI = 1: DMA priority
The priority assigned to the DMA channels determines which DMA channel per-
forms a read or write transfer first, given that two or more channels are ready to
perform transfers.
The priority of the auxiliary channel is configurable by programming the CH PRI
field in the DMA auxiliary control register. By default, CH PRI contains the value
0000b at reset. This value sets the auxiliary channel as highest priority, followed
by channel 0, followed by channel 1, followed by channel 2, with channel 3 having
lowest priority.
Arbitration between channels occurs independently every CPU clock cycle for
read and write transfers. Any channel that is in the process of waiting for syn-
chronization of any kind can lose control of the DMA controller to a lower priority
channel. Once that synchronization is received, that channel can regain control
of the DMA controller from a lower priority channel. This rule is applied indepen-
dently to the transmit and receive portions of a split mode transfer. The transmit
portion has higher priority than the receive portion.
If multiple DMA channels and the CPU are contending for the same resource,
the arbitration between DMA channels occurs first. Then, arbitration between
the highest priority DMA channel and the CPU occurs. Normally, if a channel
has lower priority than the CPU, all lower priority channels should also are low-
er priority than the CPU. Similarly, if a channel has a higher priority than the
CPU, all higher priority channels should also be higher priority than the CPU.
Resource Arbitration and Priority Configuration
5 4
AUXPRI
RW, +0
Direct Memory Access (DMA) Controller
3 0
CH PRI
RW, +0
5-31