Effect Of Mpui Endianess Conversion Settings - Texas Instruments OMAP5910 Reference Manual

DSP Subsystem Endianess
Table 89. Effect of MPUI Endianess Conversion Settings
MPU-Side Read Access to DSP-Side Data Value 0x1234 5678
Word Swap
Off
Off
On
On
10.3.2.1 MPUI Control Register (CTRL_REG)
202 DSP Subsystem
The endianess conversion unit of the MPUI is configured by the MPU core
through the MPUI control register (see section 10.3.2.1). This register contains
two configuration bit fields that control the way the endianess conversion is
handled:
The WORD_SWAP bit field determines whether word swapping is
-
performed on accesses to DSP subsystem internal memory, shared
peripherals, or both.
The BYTE_SWAP bit field determines whether byte swapping is
-
performed on accesses to DSP subsystem internal memory, shared
peripherals, or both.
The results of the different endianess settings for MPUI memory accesses are
shown in Table 89.
Byte Swap
Off
On
Off
On
When using the same access size on the MPU and the DSP, no endianess
conversion is required. In this case, both word swapping and byte swapping
should be disabled. Otherwise, word and byte swapping must be used as
specified by your application.
Typically, neither byte nor word swapping are needed when accessing the
DSP peripheral registers, as the register size is predefined.
The endianess conversion unit of the MPUI is configured by the MPU core
using the MPUI control register (CTRL_REG). The MPUI control register is
located at address 0xFFFE C900 in the memory space of the MPU core.
Figure 95 and Table 90 describe the bits in the MPUI control register that affect
the endianess of DSP subsystem accesses through the MPUI.
16-Bit Access
0x1234
0x3412
0x1234
0x3412
32-Bit Access
0x12345678
0x34127856
0x56781234
0x78563412
SPRU890A