Ifr0 And Ier0 Bit Locations (Omap5912); Ifr1 And Ier1 Bit Locations (Omap5912) - Texas Instruments OMAP5910 Reference Manual

DSP Subsystem Interrupts
Table 92. OMAP5912 Level 1 Interrupt Mapping (Continued)
Hardware C55x DSP
Interrupt Core Vector
Priority
27 RTOSIV (IV26)
28
29
30
31
32
†
NMI is not physically connected on OMAP devices, it is included here for compatibility with other C55x documentation.
Figure 100. IFR0 and IER0 Bit Locations (OMAP5912)
15 14
DMAC5 DMAC4
RW-0 RW-0
7 6
IRQ2_ L21FIQ
GPIO1
RW-0 RW-0
Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
Figure 101. IFR1 and IER1 Bit Locations (OMAP5912)
15
7 6
TIMER1 TIMER2
RW-0 RW-0
Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
212 DSP Subsystem
Vector
Address
Name (Byte Address)
IVPD:D0h
SIV27 IVPD:D8h
SIV28 IVPD:E0h
SIV29 IVPD:E8h
SIV30 IVPD:F0h
SIV31 IVPD:F8h
13 12
WDT UART3
RW-0 RW-0
5 4
MBX1 TCABORT
RW-0 RW-0
Reserved
R-0
5 4
DMAC3 DMAC2
RW-0 RW-0
Name
RTOS
SINT27
SINT28
SINT29
SINT30
SINT31
11 10
SINT11 MPU
RW-0 RW-0
3 2
L20IRQ EMUINT
RW-0 RW-0
11 10
RTOS
RW-0
3 2
MBX2 DMAC0
RW-0 RW-0
Interrupt Source
Real-time operating
system interrupt
Software interrupt #27
Software interrupt #28
Software interrupt #29
Software interrupt #30
Software interrupt #31
9 8
DMAC1 TIMER3
RW-0 RW-0
1 0
Reserved
R-0
9 8
DLOG BERR
RW-0 RW-0
1 0
L21IRQ EMIF
RW-0 RW-0
SPRU890A