First Level Interrupts - Texas Instruments OMAP5910 Reference Manual

11.2

First Level Interrupts

11.2.1 OMAP5910 First Level Interrupt Mapping and Interrupt Registers
SPRU890A
The C55x DSP core supports 32 level 1 interrupts. After receiving and
acknowledging an interrupt request, the DSP core generates an interrupt
vector address. At the vector address, the core fetches the vector that points
to the corresponding interrupt service routine (ISR). When multiple hardware
interrupts occur simultaneously, the DSP core services them one at a time,
according to their predefined hardware interrupt priorities.
Vector pointers IVPD and IVPH point to up to 32 interrupt vectors in program
space. IVPD points to the 256-byte program page for interrupt vectors 0-15
and 24-31. IVPH points to the 256-byte program page for interrupt vectors
16-23.
The DSP core supports two types of interrupts: maskable interrupts and
nonmaskable interrupts. Maskable interrupts can be blocked (masked) or
enabled (unmasked) through software. Each maskable interrupt has a
corresponding bit in an interrupt enable register (IER0 or IER1) and an
interrupt flag register (IFR0 or IFR1). Maskable interrupts include the
interrupts associated with vectors 2-23, a bus error interrupt, a data log
interrupt, and a real-time operating system interrupt.
Whenever a maskable interrupt is requested by hardware, its corresponding
interrupt flag is set in one of the interrupt flag registers. Once the flag is set,
the interrupt is not serviced unless it is enabled through the interrupt enable
registers. The ISRs for the maskable interrupts can also be executed by
software with the use of the INTR and TRAP assembly instructions.
When the DSP core receives a nonmaskable interrupt request, the DSP core
acknowledges it unconditionally and immediately branches to the
corresponding interrupt service routine (ISR). The nonmaskable interrupts
include RESET and any software interrupts initiated through the use of the
INTR and TRAP instructions.
Note:
NMI is not available on OMAP devices.
For more details on C55x DSP core interrupts, see the TMS320C55x DSP
CPU Reference Guide (SPRU371).
Table 91 shows the level 1 interrupts sorted by interrupt vector number for
OMAP5910. Figure 98 and Figure 99 show the bit layout for the IFR0/IER0
and IFR1/IER1 registers, respectively.
DSP Subsystem Interrupts
DSP Subsystem 207