Effect Of Dsp Mmu Endianess Conversion Settings - Texas Instruments OMAP5910 Reference Manual

Multimedia processor dsp subsystem
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DSP Subsystem Endianess
10.3.1
Endianess Conversion by the DSP MMU
Table 87. Effect of DSP MMU Endianess Conversion Settings
DSP-Side Read Access to MPU-Side Data Value 0x1234 5678
Conversion Enable
Disabled (EN = 0)
Enabled (EN = 1)
Enabled (EN = 1)
10.3.1.1
DSP MMU Endianess Control Register (DSP_ENDIAN_CONV)
200
DSP Subsystem
Endianess conversion is performed at the boundary between the DSP
subsystem and the DSP MMU. The endianess conversion unit of the DSP
MMU splits data accesses into individual bytes and reorders them according
to the access type and chosen configuration.
The DSP MMU endianess conversion logic is configured by the MPU core
through the DSP MMU endianess configuration register (see section
10.3.1.1). This register contains two configuration bits that control whether,
and how, endianess conversion is performed:
The first bit, EN, enables or disables endianess conversion.
-
The second bit, SWAP, selects the type of endianess conversion to be
-
performed− either swapping the 16-bit words only or swapping both the
16-bit words and the bytes within the words. Note that the 16-bit word
swapping applies only to 32-bit accesses.
Table 87 lists the effects of the different configuration settings of the DSP MMU
endianess conversion logic.
Word/Byte Swap
Don't care (SWAP = X)
Byte and word swap
(SWAP = 0)
Word swap only
(SWAP = 1)
Typically, both the 16-bit words and the bytes within each 32-bit word are
swapped if the MPU has written data using four 8-bit accesses and is read as
one 32-bit word by the DSP. In contrast, only the 16-bit words (but not the bytes
within them) are swapped when the MPU has written data in two 16-bit
accesses and the DSP reads them using one 32-bit access. No endianess
conversion is required if both the MPU and the DSP access the data as 32-bit.
The DSP MMU endianess conversion unit is configured by the MPU core using
the DSP MMU endianess control register (Figure 94 and Table 88) located at
address 0xFFFE CC34.
16-Bit Access
0x5678
0x7856
0x5678
32-Bit Access
0x1234 5678
0x7856 3412
0x5678 1234
SPRU890A

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