Emac Control Module Interrupt Control Register (Cmintctrl); Emac Control Module Interrupt Control Register (Cmintctrl) Field Descriptions - Texas Instruments TMS320DM646x User Manual

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3.4

EMAC Control Module Interrupt Control Register (CMINTCTRL)

The interrupt control register (CMINTCTRL) is shown in
Figure 16. EMAC Control Module Interrupt Control Register (CMINTCTRL)
31 30
Reserved
R/W-0
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. EMAC Control Module Interrupt Control Register (CMINTCTRL)
Bit Field
31 Reserved
30-18 Reserved
17-16 INTPACEEN
15-12 Reserved
11-0 INTPRESCALE
SPRUEQ6 – December 2007
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Reserved
12 11
Value Description
0 Reserved
0 Reserved
0-3h Interrupt pacing enable.
Bit 16 = 1; enables Rx_Pulse Pacing; = 0, disables pacing
Bit 17 = 1; enables Tx_Pulse Pacing; = 0, disables pacing
0 Reserved
0-7FFh Interrupt counter prescaler. The number of peripheral clock periods in 4 s.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Figure 16 and described in
R-0
INTPRESCALE
R/W-0
Field Descriptions
EMAC Control Module Registers
Table 13.
18 17 16
INTPACEEN
R/W-0
0
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