Idle Control Register (Icr); Registers For Dsp Module Idle Control - Texas Instruments OMAP5910 Reference Manual

12.3.2.8 Idle Registers
Table 99. Registers for DSP Module Idle Control
Name
ICR
ISTR
†
DSP I/O addresses apply to both OMAP5910 and OMAP5912.
Figure 106. Idle Control Register (ICR)
15
7 6
Reserved
R-0
†
These bits must always be 0.
Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
SPRU890A
Note:
The EMIF domain is not taken out of its idle state when the CPU domain is
woken up by a maskable interrupt. This means that if both the EMIF and CPU
domains are idle, the DSP core must not branch to the interrupt service
routine (ISR) immediately after waking up if the ISR is located in DSP
external memory. The DSP core can be kept from branching to the ISR by
keeping the INTM bit until the EMIF has been manually awakened (see
section 12.3.2.5).
Two registers provide the means to individually configure and monitor each of
the idle domains: the idle configuration register (ICR) and the idle status
register (ISTR). These registers are accessible to the DSP core only.
Description
Idle control register. Use this register to specify which domain
should be idled when the IDLE instruction is executed.
Idle status register. Use this register to check the status of
the idle domains.
ICR lets you configure how each idle domain will respond upon IDLE
instruction execution. When you execute the IDLE instruction, the content of
ICR is copied to ISTR. The ISTR values are then propagated to the idle
domains.
Reserved
5 4
EMIFI Reserved
RW-0
DSP Subsystem Reset, Clocking, Idle Control, and Boot
R-0
3 2
† CACHEI
RW-0 RW-0
DSP I/O
Address
0x0001
0x0002
8
1 0
DMAI CPUI
RW-0 RW-0
DSP Subsystem
†
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