Idle Status Register (Istr); Idle Control Register (Icr) Field Descriptions - Texas Instruments OMAP5910 Reference Manual

DSP Subsystem Reset, Clocking, Idle Control, and Boot
Table 100. Idle Control Register (ICR) Field Descriptions
Bits Field
15−6 Reserved
5 EMIFI
4-3 Reserved
2 CACHEI
1 DMAI
0 CPUI
Figure 107. Idle Status Register (ISTR)
15
7 6
Reserved
R-0
Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
226 DSP Subsystem
Value Description
− These bits are read-only and return 0s when read.
EMIF-domain idle configuration bit. EMIFI determines whether the
external memory interface (EMIF) will be idle after the next execution
of the IDLE instruction:
0 EMIF will be active.
1 EMIF will be idle.
− Must always be kept as 0.
CACHE-domain idle configuration bit. CACHEI determines whether
the cache will be idle after the next execution of the IDLE instruction:
0 Cache will be active.
1 Cache will be idle.
DMA-domain idle configuration bit. DMAI determines whether the
DMA controller will be idle after the next execution of the IDLE
instruction:
0 DMA controller will be active.
1 DMA controller will be idle.
CPU-domain idle configuration bit. CPUI determines whether the DSP
core will be idle after the next execution of the IDLE instruction:
0 DSP core will be active.
1 DSP core will be idle.
Reserved
R-0
5 4
EMIFIS Reserved
R-0 R-0
3 2
CACHEIS
R-0
8
1 0
DMAIS CPUIS
R-0 R-0
SPRU890A